1. Field of the Invention
The present invention relates to signal amplification devices, and more particularly, to a signal amplification device for amplifying an input signal by automatically setting a threshold level.
2. Description of the Related Art
High-speed large-capacity broadband optical access networks have been more and more actively constructed to keep up with an explosive increase in data traffic as typified by the Internet. Potential high-speed optical access systems include a G-PON (Gigabit-Passive Optical Network) system which shares an optical fiber network connecting subscribers and a central office and which is capable of high-speed transmission at a maximum data rate of 1 Gbps (physical rate: 1.25 Gbps).
FIG. 22 shows a schematic configuration of a G-PON system. The G-PON system 100 comprises an OLT (Optical Line Terminal) 101, a plurality of ONUs (Optical Network Units) 102-1 to 102-n, and an optical splitter 103.
The OLT 101 and the optical splitter 103 are connected by a single optical fiber, and optical fibers branching off from the optical splitter 103 are connected to the respective ONUs 102-1 to 102-n. The optical splitter 103 carries out 1:n optical splitting/coupling.
In the G-PON system 100, upstream transmission from the ONUs 102-1 to 102-n to the OLT 101 is performed by means of signals with an identical wavelength (1310 nm) sent out from the individual ONUs 102-1 to 102-n. Thus, to prevent collision of optical packets sent from different ONUs, TDMA (Time Division Multiple Access) is employed whereby the transmit timing is controlled according to time division multiplexing.
For the downstream transmission from the OLT 101 to the ONUs 102-1 to 102-n, TDM (Time Division Multiplexing) is adopted in which all ONUs 102-1 to 102-n receive the signal (wavelength: 1490 nm) from the OLT 101 and read out only the information contained in the time slots respectively assigned thereto.
In the case of the upstream transmission, the OLT 101 is synchronized with each of signals transmitted from the ONUs 102-1 to 102-n to receive and regenerate the signals.
For example, where optical packets #1 to #n are transmitted from the respective ONUs 102-1 to 102-n according to TDMA (the optical packets #1 to #n have respective different levels) as shown in FIG. 22, an optical burst-mode receiver 101a is first synchronized with the optical packet #1 to receive same. When receiving the optical packet #2 thereafter, the optical burst-mode receiver 101a is again synchronized with the optical packet #2 to receive same, because the level of the optical packet #2 is different from that of the optical packet #1. The other optical packets are received in like manner.
As conventional signal receiving/regenerating techniques, a technique is known in which the level of an EEM signal read from an optical disk is set to a predetermined level to reproduce data from the EFM signal (e.g., Japanese Patent No. 2889803 (paragraph nos. [0010] to [0015], FIG. 1)).
FIG. 23 shows the transmission format of upstream optical packets. The ONUs 102-1 to 102-n individually output optical packets as a burst, and the optical splitter 103 multiplexes the packets, which are then transmitted to the OLT 101.
In order to absorb timing offsets of the ONUs 102-1 to 102-n, a guard time (signal absence interval) is provided between adjacent optical packets. Also, at the beginning of each optical packet, a preamble is provided for the purpose of synchronization of the optical burst-mode receiver 101a of the OLT 101.
The OLT 101 receives upstream optical packets having such transmission format. When receiving the optical packet #2 after receiving the optical packet #1, for example, the optical burst-mode receiver 101a must be synchronized with the optical packet #2 during the preamble of the optical packet #2 (the guard time interval between the optical packets #1 and #2 is used for the initialization of the optical burst-mode receiver 101a).
During the upstream transmission at 1.25 Gbps, the guard time is, for example, 30 bits (24 ns) and the preamble is about 20 bits (16 ns). Also, the transmission levels of optical packets significantly differ from each other, with the result that the dynamic range becomes as large as 30 dB (1000 times) at the maximum.
It is therefore necessary that the OLT 101 should be synchronized with each of optical packets significantly varying in level depending on individual ONUs, within a short period of the guard time plus the preamble, and quicker response of the OLT 101 has been a principal objective in order to make the G-PON system 100 more practical. Moreover, to bring optical access systems into wide use, it is also necessary that the optical burst-mode receiver 101a should have a simple and cost-effective configuration. Accordingly, the circuitry of the optical burst-mode receiver 101a should desirably be fabricated using low-cost standard CMOS (Complementary Metal Oxide Semiconductor) technology.
Meanwhile, the optical burst-mode receiver 101a includes an automatic threshold circuit (ATC) therein. The auto threshold circuit is adapted to automatically set the threshold level to a median between the levels “1” and “0” of an input signal, to enable instantaneous signal discrimination (equivalent to the aforementioned synchronization with an optical packet). The auto threshold circuit comprises, as its principal components, a peak detector for detecting the level “1”, a bottom detector for detecting the level “0”, and a voltage divider for setting the threshold to a median level between the levels “0” and “1”.
FIG. 24 shows a schematic configuration of the peak detector. The peak detector 110, which is an element constituting the automatic threshold circuit, includes an amplifier 111, an N-channel MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor) 112, a buffer 113, and a capacitor C3.
The amplifier 111 has an input terminal (+) supplied with an electrical signal obtained by subjecting an optical packet to O/E conversion, and has the other input terminal (−) connected to the output terminal of the buffer 113. The output terminal of the amplifier 111 is connected to the drain and gate of the FET 112, of which the source is connected to one end of the capacitor C3 as well as to the input terminal of the buffer 113. The other end of the capacitor C3 is connected to GND (grounded). The FET 112 serves to rectify the output waveform of the amplifier 111 and plays a role equivalent to a diode; therefore, the FET is hereinafter referred to as FET diode 112.
FIG. 25 shows an ideal output waveform of the peak detector 110, wherein the horizontal axis indicates time and the vertical axis indicates voltage. When the voltage of the input signal varies on the positive side from the level “0” as a reference, the FET diode 112 conducts, charging the capacitor C3 so as to hold the maximum value of the input signal. If, in the circuit of FIG. 24, Vin drops to a level lower than Vout, the amplifier 111 outputs a negative voltage Va of large magnitude, so that the FET diode 112 is reversely biased. However, since Vout is held by the charge voltage of the capacitor C3, the output Vout is maintained and follows the maximum value (peak value) of the input Vin.
In cases where the peak detector 110 is used in a system adapted to receive signals at a high, Gbps-order data rate, such as a G-PON system, a problem arises in that it is difficult to detect peaks with high accuracy. The following explains the problems associated with the conventional peak detector 110 (e.g., a problem with the peak detector 110 that arises when the input signal varies toward the level “1” side from the level “0” as a reference).
Let us consider the amplifier 111 first. The performance of the amplifier 111 depends upon the frequency range and voltage range of the input signal. If the performance of the amplifier 111 is not up to properly handling the input signal, an error (detection error) is caused between an actual peak of the input signal and the peak detected by the peak detector 110.
FIG. 26 shows such a peak detection error, wherein the horizontal axis indicates time and the vertical axis indicates voltage. Let us suppose the case where the input signal has a waveform alternating in a high data rate and also has a small amplitude. In this case, if the frequency bandwidth of the input signal is higher than the frequency bandwidth that can be processed by the amplifier 111 and also if the gain of the amplifier 111 is insufficient, an error Δ is caused between an actual peak P1 of the input signal and a peak level P2 detected by the peak detector 110, for the reason explained below.
The amplifier 111 is a differential amplifier; therefore, the amplifier 111 amplifies a differential level corresponding to the error Δ between the actual peak P1 and the detected peak P2 and outputs a signal (hereinafter referred to as signal d1) having a waveform with a smaller amplitude than that of the input signal. If such signal d1 is output from the amplifier 111, the FET diode 112 fails to be applied with a sufficiently high voltage needed for operation.
FIG. 27 exemplifies the relationship between drain current and gate-source voltage, or the characteristic of the FET diode 112, wherein the horizontal axis indicates the drain current (A) and the vertical axis indicates the gate-source voltage (V). As seen from FIG. 27, as the gate-source voltage lowers, the drain current approaches “0”.
FIG. 28 exemplifies the relationship between drain current and differential resistance, wherein the horizontal axis indicates the drain current (mA) and the vertical axis indicates the differential resistance (Ω). As illustrated, the smaller the drain current of the FET diode 112, the greater the differential resistance becomes.
FIG. 29 shows the relationship between drain current and cut-off frequency, wherein the horizontal axis indicates the drain current (mA) and the vertical axis indicates the cut-off frequency (Hz) (where the capacitance is, e.g., 1 pF). The figure reveals that as the drain current of the FET diode 112 decreases, the cut-off frequency of the device constituted by the FET diode 112 and the capacitor C3 lowers due to increase of the differential resistance, which entails a shortage of bandwidth.
Thus, even if an amplifier with high slew rate and wide frequency bandwidth is used for the amplifier 111 in order to restrain narrowing of the bandwidth, the FET diode 112 and the capacitor C3, which are passive elements unsuited for quick response to a weak input signal with a small amplitude, are arranged in the stage succeeding the amplifier 111. Accordingly, the passive elements eventually become a bottleneck and narrow the bandwidth, giving rise to the problem that the peak voltage detection accuracy lowers.
If the peak detection accuracy of the OLT 101 is not high, then it is impossible to accurately set the threshold to the median level of the received signal.
Namely, the threshold cannot be set at the center of the eye pattern, with the result that codes may possibly be recognized in error (e.g., “1” may possibly be mistaken for “0”), which lowers reliability.
Further, in cases where the input signal begins to show a continuously high waveform subsequently to an alternating waveform, the peak detection error decreases to a small level upon start of the continuously high waveform, compared with that caused during the alternating waveform interval, posing the problem that the threshold varies even though the input signal being received is of the same level.
FIG. 30 shows such variation of the threshold caused when the input signal begins to show a continuously high waveform subsequently to an alternating waveform, wherein the horizontal axis indicates time and the vertical axis indicates voltage. While the input signal shows an alternating waveform in a high data rate, narrowing of the bandwidth takes place in the peak detector 110, causing the peak detection error Δ shown in FIG. 26. As the input signal begins to show a continuously high waveform thereafter, the frequency bandwidth of the input signal becomes lower than the cut-off frequency of the device constituted by the FET diode 112 and the capacitor C3, whereby the peak detector can follow up the peak of the input signal and output a nearly accurate peak value.
This means that the threshold varies during the reception of one optical packet. If the threshold varies, erroneous recognition of codes may possibly take place in a manner such that, for example, before the variation of the threshold, a certain code is recognized as “1”, but after the threshold variation, the same code is recognized as “0”, lowering the reliability of the code reproduction by the OLT 101.